STM32F767IIT6

The TMS320x240xA devices use an advanced Harvard-type architecture that maximizes processing power bymaintaining two separate memory bus structures — program and data — for full-speed execution. This multiplebus structure allows data and instructions to be read simultaneously. Instructions support data transfersbetween program memory and data memory. This architecture permits coefficients that are stored in programmemory to be read in RAM, thereby eliminating the need for a separate coefficient ROM. This, coupled with afour-deep pipeline, allows the LF240xA/LC240xA devices to execute most instructions in a single cycle. Seethe functional block diagram of the 240xA DSP CPU for more information.TMS320x240xA instruction setThe x240xA microprocessor implements a comprehensive instruction set that supports both numeric-intensive**-processing operations and general-purpose applications, such as multiprocessing and high-speedcontrol.For maximum throughput, the next instruction is prefetched while the current one is being executed. Becausethe same data lines are used to communicate to external data, program, or I/O space, the number of cycles aninstruction requires to execute varies, depending upon whether the next data operand fetch is from internal orexternal memory. Highest throughput is achieved by maintaining data memory on chip and using either internalor fast external program memory.